基于FPGA的等精度数字频率计的设计与实现

component TESTCTL is                         //调用测频控制信号发生器(TESTCTL)
      port( CLK:in std_logic;
           TSTEN:out std_logic;
           CLR_CNT:out std_logic;
           Load: out std_logic);
end component;

component CNT10 is         //调用有时钟使能的十进制计数器(CNT10)
     port(CLK:in std_logic;
          CLR:in std_logic;
          ENA:in std_logic;
          CQ:out std_logic_vector(3 downto 0);
          CARRY_OUT:out std_logic);
end component;

component REG32B is                       //调用32位锁存器(REG32B)
    port(Load:in std_logic;
         Din:in std_logic_vector(31 downto 0);
         Dout:out std_logic_vector(31 downto 0));
end component;

component LED7 is                          //调用7段显示译码器(LED7)
     port(sin:in std_logic_vector(3 downto 0);
          dout:out std_logic_vector(6 downto 0));
end component;
signal TSTEN1: std_logic;
signal CLR_CNT1: std_logic;
signal Load1: std_logic;
signal Din: std_logic_vector(31 downto 0);
signal Dout1: std_logic_vector(31 downto 0);
signal CARRY_OUT1: std_logic;
signal CARRY_OUT2: std_logic;
signal CARRY_OUT3: std_logic;
signal CARRY_OUT4: std_logic;
signal CARRY_OUT5: std_logic;
signal CARRY_OUT6: std_logic;
signal CARRY_OUT7: std_logic;
signal CO: std_logic;

Begin    //元件例化，即各个模块的连接
u1:TESTCTL port map(Fsin=>Fsin,CLK=>CLK,TSTEN=>TSTEN1,
CLR_CNT=>CLR_CNT,Load=>Load1);
u2:CNT10 port map(CLK=>FSIN,CLR=>CLR_CNT1,ENA=>TSTEN1,
CARRY_OUT=>CARRY_OUT1,CQ=>Din(3 downto 0));
  u3: CNT10 port map(CLK=>CARRY_OUT1,CLR=>CLR_CNT1,ENA=>TSTEN1,                      CARRY_OUT=>CARRY_OUT2,CQ=>Din(7 downto 4));                  
  u4: CNT10 port map(CLK=>CARRY_OUT2,CLR=>CLR_CNT1,ENA=>TSTEN1,                     CARRY_OUT=>CARRY_OUT3,CQ=>Din(11 downto 8));       
u5: CNT10 port map(CLK=>CARRY_OUT3,CLR=>CLR_CNT1,ENA=>TSTEN1,                     CARRY_OUT=>CARRY_OUT4,CQ=>Din(15 downto 12));       
u6: CNT10 port map(CLK=>CARRY_OUT4,CLR=>CLR_CNT1,ENA=>TSTEN1,                     
CARRY_OUT=>CARRY_OUT5,CQ=>Din(19 downto 16));       
u7: CNT10 port map(CLK=>CARRY_OUT5,CLR=>CLR_CNT1,ENA=>TSTEN1,                      CARRY_OUT=>CARRY_OUT6,CQ=>Din(23 downto 20));
  u8: CNT10 port map(CLK=>CARRY_OUT6,CLR=>CLR_CNT1,ENA=>TSTEN1,                      CARRY_OUT=>CARRY_OUT7,CQ=>Din(27 downto 24));       
  u9: CNT10 port map(CLK=>CARRY_OUT7,CLR=>CLR_CNT1,ENA=>TSTEN1,                      CARRY_OUT=>CO,CQ=>Din(31 downto 28));  
  u10: REG32B port map(Load=>Load1,Din=>Din,Dout=>Dout1);
u11: LED7 port map(sin=>Dout1(31 downto 28),dout=>AA);
  u12: LED7 port map(sin=>Dout1(27 downto 24),dout=>BB);
  u13: LED7 port map(sin=>Dout1(23 downto 20),dout=>CC);
  u14: LED7 port map(sin=>Dout1(19 downto 16),dout=>DD);转贴于 酷文网-论文下载中心 http://www.coolwen.net